ECE 624: DIG SYS AUTO VHDL
California State University, Northridge
Prerequisite: ECE 623 or instructor consent. Issues related to CAD tools used in the physical design of VLSI systems. A discussion of the mathematical tools used in this field, such as graph theory, optimization and search techniques, such as mathematical programming, and defining the constraints and objectives associated with each problem, as well as several classical algorithms used in their solution. These problems include floorplanning, partitioning, placement and routing. Discussion of static timing analysis and signal integrity, leading to development of new CAD tools for Deep Sub-micron technology.
Average GPA: 3.62
Grade distribution records: 25 students across 2 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A | 10 | 40.0% |
| A- | 5 | 20.0% |
| B+ | 7 | 28.0% |
| B | 3 | 12.0% |
Based on 25 student grade records across 2 terms and 1 professor.
Instructors
- Ramin Roosta 25 students, Average GPA 3.62