EE 168: INTRODUCTION TO VERY LARGE SCALE INTEGRATION DESIGN
University of California, Riverside
4 Units, Lecture, 3 hours; laboratory, 3 hours. Prerequisite(s): CS 120A or EE 120A; or consent of instructor. Studies integrated circuit fabrication, device characterization, and circuit simulation. Introduces basic device physics and physical design rules, MOS logic design, and timing and clock schemes. Covers layout generation, subsystem designs, and circuits for alternative logic styles. Also covers design and simulation using hardware description language and CAD tools. Cross-listed with CS 168. Credit is awarded for one of the following EE 168, CS 168, or EE 282A.
Average GPA: 3.35
Grade distribution records: 229 students across 9 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A+ | 22 | 9.6% |
| A | 43 | 18.8% |
| A- | 62 | 27.1% |
| B+ | 41 | 17.9% |
| B | 22 | 9.6% |
| B- | 13 | 5.7% |
| C+ | 6 | 2.6% |
| C | 5 | 2.2% |
| C- | 6 | 2.6% |
| D+ | 2 | 0.9% |
| D | 1 | 0.4% |
| F | 5 | 2.2% |
| NP | 1 | 0.4% |
Based on 229 student grade records across 9 terms and 1 professor.
Instructors
- Sheldon Tan 156 students, Average GPA 3.25