ECE 122B: VLSI ARCH/DESIGN
University of California, Santa Barbara
Practical issues in VLSI circuit design, pad/pin limitations, clocking and interfacing standards, electrical packaging for high-speed and high-performance design. On-chip noise and crosstalk, clock and power distribution, architectural and circuit design constraints, interconnection limits and transmission line effects.
Average GPA: 3.24
Grade distribution records: 64 students across 7 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A+ | 6 | 9.4% |
| A | 16 | 25.0% |
| A- | 10 | 15.6% |
| B+ | 7 | 10.9% |
| B | 16 | 25.0% |
| B- | 2 | 3.1% |
| C | 2 | 3.1% |
| D | 2 | 3.1% |
| F | 3 | 4.7% |
Based on 64 student grade records across 7 terms and 1 professor.
Instructors
- Brewer F 64 students, Average GPA 3.24