Verilog digital logic design with emphasis on ASIC and FPGA design. Students design and verify large-scale systems. Assignments and project use the Verilog Hardware Description Language with emphasis on verification and high-frequency ASIC/FPGA targets. May be taught in conjunction with CSE 225. Students cannot receive credit for both courses.
7 terms
Other grades
University of California, Santa Cruz
CSE 125 at UCSC: average GPA 3.45 across 297 students. Grade distribution by term. Verilog digital logic design with emphasis on ASIC and FPGA design. Students…
Average GPA: 3.45
Grade distribution records: 297 students across 7 terms.
| Grade | Students | Percent |
|---|---|---|
| A+ | 35 | 11.8% |
| A | 83 | 27.9% |
| A- | 54 | 18.2% |
| B+ | 30 | 10.1% |
| B | 24 | 8.1% |
| B- | 15 | 5.1% |
| C+ | 11 | 3.7% |
| C | 6 | 2.0% |
| D+ | 4 | 1.3% |
| F | 6 | 2.0% |
| P | 8 | 2.7% |
| NP | 9 | 3.0% |
| S | 1 | 0.3% |
| W | 9 | 3.0% |
Based on 297 student grade records across 7 terms and 3 professors.
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