CSE 225: Asic Systems Design
University of California, Santa Cruz
Verilog digital logic design with emphasis on ASIC and FPGA design. Students design and verify large-scale systems. Assignments and project use the Verilog Hardware Description Language with emphasis on verification and high-frequency ASIC/FPGA targets. Course may be taught in conjunction with CSE 125.
Average GPA: 3.62
Grade distribution records: 81 students across 4 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A+ | 11 | 13.6% |
| A | 27 | 33.3% |
| A- | 16 | 19.8% |
| B+ | 6 | 7.4% |
| B | 7 | 8.6% |
| B- | 4 | 4.9% |
| C+ | 1 | 1.2% |
| C | 1 | 1.2% |
| D | 1 | 1.2% |
| NP | 1 | 1.2% |
| S | 3 | 3.7% |
| U | 3 | 3.7% |
Based on 81 student grade records across 4 terms and 2 professors.
Instructors
- Dustin Richmond 66 students, Average GPA 3.61
- Ethan Sifferman 15 students, Average GPA 3.67