ECE 520: SOC DESIGN
California State University, Northridge
Prerequisites: ECE 420, ECE 425. Corequisite: ECE 520L. Introduction to system on chip design methodology that includes the study of ZYNQ and ARM architectures, AXI Interconnect, memory, real-time operating system (RTOS), peripheral interface and components, and contemporary high-density FPGAs.
Average GPA: 3.89
Grade distribution records: 290 students across 8 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A | 260 | 89.7% |
| A- | 13 | 4.5% |
| B+ | 5 | 1.7% |
| B | 4 | 1.4% |
| C+ | 2 | 0.7% |
| C | 2 | 0.7% |
| D | 3 | 1.0% |
| F | 1 | 0.3% |
Based on 290 student grade records across 8 terms and 1 professor.
Instructors
- Saba Janamian 265 students, Average GPA 3.88