ECE 520L: SOC DESIGN LAB
California State University, Northridge
Prerequisites: ECE 420, ECE 425. Corequisite: ECE 520. This laboratory course reinforces the system-on-chip design concept developed in the lecture course. It focuses on software hardware co-design and development and hardware verification of ZYNQ systems using Vivado software tools and ZYNQ development boards.
Average GPA: 3.88
Grade distribution records: 291 students across 8 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A | 260 | 89.3% |
| A- | 9 | 3.1% |
| B+ | 7 | 2.4% |
| B | 7 | 2.4% |
| C+ | 2 | 0.7% |
| C | 2 | 0.7% |
| D | 3 | 1.0% |
| F | 1 | 0.3% |
Based on 291 student grade records across 8 terms and 1 professor.
Instructors
- Saba Janamian 266 students, Average GPA 3.87