CMPE 140: Computer Architecture and Design

San Jose State University

Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. Prerequisite: CMPE 125 (with grade of "C-" or better), Computer Engineering or Software Engineering Majors Only. Misc/Lab: Lecture 2 hours/lab 3 hours.

Average GPA: 3.02

Grade distribution records: 928 students across 16 terms.

Grade distribution

GradeStudentsPercent
A+12213.1%
A13714.8%
A-849.1%
B+11011.9%
B14715.8%
B-646.9%
C+525.6%
C12213.1%
C-535.7%
D+70.8%
D171.8%
D-30.3%
F101.1%

Based on 928 student grade records across 16 terms and 6 professors.

Instructors

Still loading. This can take a moment on a slow connection.

Loading My Class Grades