EE 118: Digital Logic Circuit Design
San Jose State University
Fundamentals of digital logic design. Boolean logic, MUXes, DEMUXes, decoders, encoders, comparators, arithmetic blocks, flip-flops, counters, registers, RAMs/ROMs, PLDs and FPGAs. Design of a simple computer CPU. Schematic capture and Hardware Description Language (HDL), particularly, Verilog. Lecture 3 hours/lab 3 hours. Prerequisite(s): EE 97 and EE 98 both with grades of "C-" or better. Allowed Declared Major: Electrical Engineering.
Average GPA: 2.50
Grade distribution records: 1,174 students across 16 terms.
Grade distribution
| Grade | Students | Percent |
|---|---|---|
| A+ | 7 | 0.6% |
| A | 168 | 14.3% |
| A- | 50 | 4.3% |
| B+ | 79 | 6.7% |
| B | 216 | 18.4% |
| B- | 81 | 6.9% |
| C+ | 131 | 11.2% |
| C | 211 | 18.0% |
| C- | 63 | 5.4% |
| D+ | 31 | 2.6% |
| D | 43 | 3.7% |
| D- | 7 | 0.6% |
| F | 87 | 7.4% |
Based on 1,174 student grade records across 16 terms and 3 professors.
Instructors
- Jeonghee Kim 612 students, Average GPA 2.39
- Chang Y Choo 431 students, Average GPA 2.59
- Tri Caohuu 131 students, Average GPA 2.71